As illustrated in FIG. 7, a conventional semiconductor device having a non-volatile memory includes a memory cell in which a pair of impurity regions 115 are formed embracing a channel region on the main surface of a semiconductor substrate 110, a selection gate electrode 112 is formed on the channel region via a gate insulating film 111, and sidewall-shaped control gate electrodes 114 are formed via gate isolation insulating films 113 (e.g., ONO film) on both side surfaces of the selection gate electrode 112 and on the surface of the channel region (the channel region in the area between each of the impurity regions 115 and the selection gate electrode 112). Silicon oxide file 117 is further formed on the control gate 114 as a protective insulating film. When the cell is selected by supplying the selection gate electrode 112 with a prescribed potential in such a semiconductor memory device, controlling the potential supplied to each of the impurity regions 115 and to each of the control gate electrodes 114 makes it possible to write in data by causing electric charge to accumulate in the gate isolation insulating film 113 beneath the control gate electrodes 114, to read out the data and to erase the data by dispelling the electric charge from the gate isolation insulating film 113.
In an impurity region connected to a gate line in a semiconductor device having such a non-volatile memory, there are cases where a portion connected to a contact plug is silicided in order to lower the resistance value. When an impurity region is silicided, there are instances where a short circuit develops between a control gate electrode and the impurity region if a coating comprising a protective insulating film that protects the control gate electrode is inadequate. As an example of a technique for preventing such short-circuiting of the control gate electrode (control gate) and impurity region (impurity diffusion layer) ascribable to silicidation, Patent Document 1 discloses using an SiON film 213, which is resistant to “light” etching (wet etching employing a hydrofluoric acid solution) as the protective insulating film (sidewall protecting film) for covering the control gate electrode (control gate CG) (see FIG. 8).
[Patent Document 1] Japanese Patent Kokai Publication No. JP-P2004-247521A